Cell architecture based on multi-gate vertical field effect transistor

ABSTRACT

A cell architecture is provided. A cell architecture including a vertical field effect transistor (VFET) having at least two fins serving as a vertical channel, a gate including a first gate portion surrounding the first fin, a second gate portion surrounding the second fin, and a third gate portion providing connection therebetween, and a top source/drain (S/D) including a first top S/D portion on the first fin and a second top S/D portion on the second fin, a gate contact structure connected to the third gate portion, a top S/D contact structure connected to one of the first top S/D portion or the second top S/D portion and serving as a horizontal conductive routing layer; and metal patterns on the gate contact structure and the top S/D contact structure and connected thereto through vias, and serving as a vertical conductive routing layer may be provided.

CROSS-REFERENCE TO RELATED APPLICATION

This non-provisional application is a continuation of U.S. applicationSer. No. 16/257,890, filed on Jan. 25, 2019, which claims priority under35 U.S.C. § 119 to U.S. Provisional Patent Application No. 62/685,340filed on Jun. 15, 2018 in the U.S. Patent and Trademark Office, thecontents of each of which are incorporated herein by reference in theirentirety.

BACKGROUND 1. Field

Some example embodiments of the inventive concepts disclosed hereinrelate to cell architectures based on vertical field effect transistors(VFETs) including two or more fins, and/or manufacturing methodsthereof.

2. Description of the Related Art

In the semiconductor industry, the term “gear ratio” (GR) refers to theratio between gate and vertical metal layer pitches. GR affects pinaccessibility, routability, and/or cell density characteristics.

Conventional planar or horizontal field effect transistors (e.g., aplanar field effect transistor, a horizontal fin field effect transistor(horizontal FinFET), or a horizontal nanosheet field effect transistor(HNS FET)) generally provide a gear ratio of 1:1. To improve GR, astandard cell architecture based on such planar or horizontal fieldeffect transistors use a vertical metal routing layer in addition to ahorizontal metal routing layer. Thus, manufacturing complexity andproduction cost for the standard cell architecture increases.

A cell architecture that has an improved GR (meaning a GR of m:n, wherem and n are natural numbers and n is greater than m) and can beimplemented without using an additional metal routing layer is highlydesired.

SUMMARY

Some example embodiments of the inventive concepts disclosed hereinrelate to a standard cell implanted based on one or more multi-gatevertical field effect transistors (VFETs).

Some example embodiments of the inventive concepts disclosed hereinrelate to a cell architecture based on multi-gate vertical field effecttransistors (VFETs) including two or more fins.

Some example embodiments of the inventive concepts disclosed hereinrelate to a standard cell having a gear ratio of m:n, where m and n arenatural numbers and n is greater than m.

According to an example embodiment of the inventive concepts, a cellarchitecture includes a VFET including a first fin and a second finprotruding from a substrate, the first fin and the second fin spacedapart from each other in a first direction and elongated in a seconddirection crossing the first direction, a gate including a first gateportion on a sidewall of the first fin, a second gate portion on asidewall of the second fin, and a third gate portion connecting thefirst gate portion with the second gate portion, and a top S/D includinga first top S/D portion at a top of the first fin and a second top S/Dportion at a top of the second fin, a gate contact structure spacedapart from the first fin and the second fin in the second direction whenviewed in a plan view and connected to the third gate portion, a top S/Dcontact structure connected to one of the first top S/D portion or thesecond top S/D portion, at least one of the top S/D contact structure orthe gate contact structure serving as a first conductive routing layerin the first direction, and metal patterns on the gate contact structureand the top S/D contact structure, the metal patterns configured to beconnected to at least one of the gate contact structure or the top S/Dcontact structure through vias, respectively, the metal patterns servingas a second conductive routing layer in the second direction

According to an example embodiment of the inventive concepts, a cellarchitecture includes a multi-gate vertical field effect transistorincluding a first fin and a second fin protruding from a substrate, thefirst fin and the second fin spaced apart from each other in a firstdirection and elongated in a second direction crossing the firstdirection, a bottom S/D on the substrate, the bottom S/D surrounding thefirst fin and the second fin, a gate including a first gate portion on asidewall of the first fin, a second gate portion on a sidewall of thesecond fin, and a third gate portion connecting the first gate portionwith the second gate portion, the third gate portion overlapping an endregion of the bottom S/D and including an extension area extending awayfrom the first and second fins in the second direction when viewed in aplan view, a top S/D including a first top S/D portion at a top of thefirst fin and a second top S/D portion at a top of the second fin, thebottom S/D in the substrate, a gate contact structure connected to thethird gate portion at the extension area of the third gate portion, atop S/D contact structure connected to one of the first top S/D portionor the second top S/D portion, at least one of the gate contactstructure or the top S/D contact structure serving as a first conductiverouting layer in the first direction, and metal patterns on the gatecontact structure and the top S/D contact structure, the metal patternsconfigured to be connected to at least one of the gate contact structureor the top S/D contact structure through vias, the metal patternsserving as a second conductive routing layer, in the second direction.

According to an example embodiment of the inventive concepts, a standardinverter cell architecture includes a PMOS vertical field effecttransistor (PMOS FET) including a first fin and a second fin protrudingfrom a substrate, the first fin and the second fin spaced apart fromeach other in a first direction and elongated in a second directioncrossing the first direction, a first gate including a first gateportion on a sidewall of the first fin and a second gate portion on asidewall of the second fin, a first top S/D including a first top S/Dportion at a top of the first fin and a second top S/D portion at a topof the second fin, an NMOS vertical field effect transistor (NMOS VFET)including a third fin and a fourth fin protruding from the substrate,the third fin and the fourth fin spaced apart from each other in thefirst direction and elongated in the second direction in the seconddirection, a second gate including a third gate portion on a sidewall ofthe third fin and a fourth gate portion on a sidewall of the fourth fin,and a second top S/D including a third top S/D portion at a top of thethird fin and a fourth top S/D portion at a top of the fourth fin, agate connecting structure at an area between the PMOS VFET and the NMOSVFET and connecting the first, second, third, and fourth gate portionsto each other, the gate connecting structure having a shape enclosingfour ends of the first, second, third, and fourth fins, which face eachother in at least one of the first direction, the second direction, or athird direction diagonal with respect to the first direction and thesecond direction, top S/D contact structures connected to the second topS/D contact portion and the fourth top S/D contact portion,respectively, a gate contact structure connected to the gate connectingstructure and laterally away from the top S/D contact structures in thefirst direction, at least one of the top S/D contact structures or thegate contact structure serving as a first conductive routing layer inthe first direction, and metal patterns configured to be connected to atleast one of the gate contact structure, the second top S/D portion, orthe fourth top S/D portion through vias, the metal patterns serving as asecond conductive routing layer in the second direction.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and effects of inventive conceptswill become more apparent to those of ordinary skill in the art bydescribing in detail example embodiments thereof with reference to theaccompanying drawings, in which:

FIGS. 1A and 1B shows gate-metal layouts of standard cell architectureshaving gear ratios of 2:3 and 3:4, respectively, according to someexample embodiments of the present inventive concepts;

FIG. 2 illustrate a equivalent circuit of an inverter X1 standard cell,according to an example embodiment of the present inventive concepts;

FIG. 3 is a layout of the inverter X1 standard cell of FIG. 2 having agear ratio of 2:3, according to an example embodiment of the presentinventive concepts;

FIG. 4 is a cross-section view of the inverter of FIG. 3 taken alongline IV-IV′, according to an example embodiment of the present inventiveconcepts;

FIG. 5 is a cross-section view of the inverter of FIG. 3 taken alongline V-V′, according to an example embodiment of the present inventiveconcepts;

FIGS. 6A-6G are layouts to explain a method of manufacturing theinverter X1 standard cell of FIGS. 3-5, according to an exampleembodiment of the present inventive concepts;

FIG. 7A is a first modified layout of the inverter X1 standard cell ofFIG. 3, according to an example embodiment of the present inventiveconcepts;

FIG. 7B is a cross-sectional view of the modified layout of FIG. 7Ataken along line VIIB-VIIB′, according to an example embodiment of thepresent inventive concepts.

FIG. 8 is a second modified layout of the inverter X1 standard cell ofFIG. 3, according to an example embodiment of the present inventiveconcepts;

FIG. 9A is a third modified layout of the inverter X1 standard cell ofFIG. 3, according to an example embodiment of the present inventiveconcepts;

FIG. 9B is a cross-sectional view of the modified layout of FIG. 9Ataken along line IXB-IXB′, according to an example embodiment of thepresent inventive concepts.

FIG. 10A is a fourth modified layout of the inverter X1 standard cell ofFIG. 3, according to an example embodiment of the present inventiveconcepts; and

FIG. 10B is a cross-sectional view of the modified layout of FIG. 10Ataken along line XB-XB′, according to an example embodiment of thepresent inventive concepts.

DETAILED DESCRIPTION

Various example embodiments will be described more fully hereinafterwith reference to the accompanying drawings, in which some exampleembodiments are shown. The present inventive concepts may, however, beembodied in many different forms and should not be construed as limitedto the example embodiments set forth herein. Rather, these exampleembodiments are merely provided so that this disclosure will be thoroughand complete, and will fully convey the scope of example embodiments tothose skilled in the art. In the drawings, the sizes and relative sizesof the various layers and regions may have been exaggerated for clarity.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present.

As used herein, the term “and/or” includes any and all combinations ofone or more of the associated listed items. Expressions such as “atleast one of,” when preceding a list of elements, modify the entire listof elements and do not modify the individual elements of the list. Thus,for example, both “at least one of A, B, or C” and “A, B, and/or C”means either A, B, C or any combination thereof. (Expressions such as“at least one of,” when preceding a list of elements, modify the entirelist of elements and do not modify the individual elements of the list.)

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belong. Itwill be further understood that terms, such as those defined incommonly-used dictionaries, should be interpreted as having a meaningthat is consistent with their meaning in the context of the relevant artand will not be interpreted in an idealized or overly formal senseunless expressly so defined herein.

Hereinafter, some example embodiments of the present inventive conceptswill be explained with reference to the accompanying drawings.

FIGS. 1A and 1B shows gate-metal layouts of standard cell architectureshaving gear ratios of 2:3 and 3:4, respectively, according to someexample embodiments of the present inventive concepts.

Referring to FIG. 1A, 9 metal layer routing patterns MP are disposed tocorrespond to 6 gate patterns GP in a unit area. The gate patterns GPmay include a first gate portion GP1, a second gate portion GP2, a thirdgate portion GP3, and a fourth gate portion GP4, as illustrated in FIG.3, and may be collectively referred to as gate portions. Thus, a gearration between the GP to MP pitches is 2:3. Referring to FIG. 1B, 6metal layer routing patterns MP are disposed to correspond to 8 gatepatterns GP in a unit area. Thus, a gear ration between the GP to MPpitches is 3:4. Although FIGS. 1A and 1B illustrate examples having 2:3and 3:4 gear ratios, example embodiments of the present inventiveconcepts are not limited thereto. According to some example embodiments,gear ratios of 1:2 or other may be implemented.

FIG. 2 illustrate an equivalent circuit of an inverter X1 standard cell,according to an example embodiment of the present inventive concepts.

Referring to FIG. 2, the inverter 1X standard cell includes an NMOSfield effect transistor (NMOS FET) and a PMOS field effect transistor(PMOS FET). Both gates of the PMOS FET and NMOS FET are commonlyconnected to an input node Vin, one source/drain (S/D) region of thePMOS FET is connected to a power supply Vdd, the other S/D region of thePMOS FET and one S/D region of NMOS FET are connected to each other andare commonly connected to an output node Vout, the other S/D region ofthe NMOS FET is connected to ground. According to some exampleembodiments of the present inventive concepts, the NMOS FET and the PMOSFET of the inverter X1 standard cell are implemented by multi-gatevertical field effect transistors (VFETs), as described in detail hereinbelow.

FIG. 3 is a layout of the inverter X1 standard cell of FIG. 2 having agear ratio of 2:3, according to an example embodiment of the presentinventive concepts. In this layout, the upper half corresponds to thePMOS FET of FIG. 2 and the lower half corresponds to the NMOS FET ofFIG. 2.

Referring to FIG. 3, a plurality of fins (e.g., a first fin F1, a secondfin F2, a third fin F3, and a fourth fin F4) are provided. The fins F1,F2, F3, and F4 are structures protruding from a substrate SUB. In someexample embodiments, the fins F1, F2, F3, and F4 may be provided bygrowing epitaxial structures at desired positions on the semiconductorsubstrate SUB.

The first fin F1 and the second fin F2 protrudes from the substrate SUB,are spaced apart from each other in a first direction D1, and areelongated in the second direction D2 crossing (or alternatively,perpendicular to) the first direction D1. The first fin F1 and a secondfin F2 collectively function as a channel of the PMOS FET.

The third fin F3 and the fourth fin F4 protrudes from the substrate SUB,are spaced apart from each other in the first direction D1, and areelongated in the second direction D2. The third fin F3 and the fourthfin F4 collectively function as a channel of the NMOS FET. Asillustrated, the first fin F1 and the third fin F3 are spaced apart fromeach other in the second direction D2, and the second fin F2 and thefourth fin F4 are spaced apart from each other in the second directionD2.

A first bottom S/D region RX1 and the second bottom S/D region RX2(collectively, referred to as first bottom S/D regions RX) are providedon the semiconductor substrate SUB. The bottom S/D regions RX1 and RX2may be doped differently. For example, the bottom S/D region RX1 in thePMOS FET area may be doped by a p-type dopants (e.g., Boron), and thebottom S/D region RX2 in the NMOS FET area may be doped by an n-typedopants (e.g., Arsenic or Phosphorus).

The first bottom S/D region RX1 (e.g., a layout pattern of the firstbottom S/D region RX1) encloses the first fin F1, the second fin F2, asubstantial or most portion of the first gate portion GP1, and asubstantial or most portion of the second gate portion GP2 when viewedin a plan view. The second bottom S/D region RX2 (e.g., a layout patternof the second bottom S/D region RX2) encloses the third fin F3, thefourth fin F4, a substantial or most portion of the third gate portionGP3, and a substantial or most portion of the fourth gate portion GP4when viewed in a plan view.

The first gate pattern GP1, the second gate pattern GP2, the third gatepattern GP3, and the fourth gate pattern GP4 may be formed on sidewallsof the fins F1, F2, F3, and F4, respectively. For example, the gatepatterns GP may be formed to surround sidewall of the fins F1, F2, F3,and F4, respectively. The first gate pattern GP1, a second gate patternGP2, a third gate pattern GP3, and a fourth gate patter GP4 may becollectively referred to as gate patterns GP.

The gate patterns GP each include a gate insulating layer (not shown)and a work function metal layer (not shown) on the gate insulating layer(not shown). In some example embodiments, the gate patterns GP mayfurther include a capping metal layer (not shown) on the work functionmetal layer.

The gate connecting structure PB may be provided to connect the firstgate pattern GP1, the second gate pattern GP2, the third gate patternGP3, and the fourth gate pattern GP4 to each other. The gate connectingstructure PB and the first gate pattern GP1, the second gate patternGP2, the third gate pattern GP3, and the fourth gate pattern GP4 mayform an integral structure, which includes respective portionscorresponding to the gate connecting structure PB and the first gatepattern GP1, the second gate pattern GP2, the third gate pattern GP3,and the fourth gate pattern GP4.

Although not shown in this layout, a first top S/D region (not shown), asecond top S/D region (not shown), a third top S/D region (not shown), afourth top S/D region (not shown) may be provided on the first, second,third, and fourth fins F1, F2, F3, and F4, respectively.

A first top S/D contact structure CA1 may be provided to cover both aportion of the first top S/D region on the first fin F1 and a portion ofthe second top S/D region on the second fin F2, and to be connected toboth the first top S/D region on the first fin F1 and the second top S/Dregion on the second fin F2. A second top S/D contact structure CA2 maybe provided to cover both a portion of the third top S/D region on thethird fin F3 and a portion of the fourth top S/D region on the fourthfin F4, and to be connected to both the third top S/D region on thethird fin F3, and on the fourth top S/D region on the fourth fin F3.

The first top S/D contact structure CA1 may be connected to the firsttop S/D region and the second top S/D region. The second top S/D contactstructure CA2 may be connected to the third top S/D region and thefourth top S/D region. The first top S/D contact structure CA1 and thesecond top S/D contact structure CA2 may be elongated in the firstdirection D1 (e.g., a direction along which the first fin F1 and thesecond fin F2 (as well as the third fin F3 and the fourth fin F4) arearranged). The first top S/D contact structure CA1 and the second topS/D region CA1 may be collectively referred to as top S/D contactstructures CA.

Accordingly, the first top S/D contact structure CA1 and the second topS/D contact structure CA2 may function as a horizontal conductiverouting layer (or alternatively, a first conductive routing layerrunning in the first direction D1) of the layout.

A gate contact structure CB may be provided on the gate connectingstructure PB such that the gate contact structure CB is connected to thegate connecting structure PB. Referring to the example embodimentillustrated in FIG. 3, the gate contact structure CB is provided on thegate connecting structure PB at an area between the first fin F1 and thethird fin in the second direction D2. The gate contact structure CB maybe spaced apart from the first, second, third, and fourth fin F1, F2,F3, and F4 when viewed in a plan view, while being connected to the gateconnecting structure PB.

A first bottom S/D contact structure CR1 may be provided on the firstbottom S/D region RX1 to contact the first bottom S/D region RX1. Asecond bottom S/D contact structure CA2 may be provided on the secondbottom S/D region RX2 to contact the second bottom S/D region RX2. Thefirst bottom S/D contact structure CR1 and the second bottom S/D contactstructure CR2 may be collectively referred to as bottom S/D contactstructures CR.

All or some of a plurality of metal patterns MP may be connected tocorresponding ones of the gate contact structure CB and the first andsecond top S/D contact structures CA1 and CA2 through corresponding onesof a plurality of vias V0, respectively. The plurality of metal patternsMP may be elongated in the second direction D2 (e.g., an elongationdirection of the fins F1, F2, F3, and F4). Thus, the plurality of metalpatterns MP may function as a vertical conductive routing layer (oralternatively, a second conductive routing layer running in the seconddirection D2) of the layout.

Accordingly, an inverter X1 standard cell including the PMOS FET and theNMOS FET each having a vertical channel implemented by two fins may beprovided. In other words, an inverter X1 standard cell includingmulti-gate NMOS VFET and multi-gate PMOS VFET may be provided. AlthoughFIG. 3 illustrates an example in which each of the respective channelsare provided to include two fins, example embodiments of the presentinventive concepts are not limited thereto. According to some exampleembodiments, a vertical channel of a VFET may be implemented by three ormore fins.

FIG. 4 is a cross-section view of the inverter of FIG. 3 taken alongline IV-IV′, according to an example embodiment of the present inventiveconcepts. FIG. 5 is a cross-section view of the inverter of FIG. 3 takenalong line V-V′, according to an example embodiment of the presentinventive concepts.

Referring to FIGS. 4 and 5, the bottom S/D regions RX are surrounded by(or are isolated from each other by), for example, shallow trenchisolation regions STI on the substrate SUB. The first gate pattern GP1surrounds a sidewall of the first fin F1. The third gate pattern GP3surrounds a sidewall of the third fin F3. Lower surfaces of the firstgate pattern GP1, the third gate pattern GP3, and the gate connectingstructure PB are insulated from the substrate SUB by a bottom spacerlayer 51. Upper surfaces of the first gate pattern GP1 and the thirdgate pattern GP3 are insulated by an upper spacer layer S2. Further,interlayer dielectric layers ILD1, ILD2, ILD3, and ILD4 (collectively,referred to as ILD) may be formed to provide proper insulation betweenconductive layers. The interlayer dielectric layers ILD1, ILD2, ILD3,and ILD4 may include a nitride material or an oxide material dependingon desired etching and/or insulation characteristics.

FIGS. 6A-6G are layouts to explain a method of manufacturing theinverter X1 standard cell of FIGS. 3-5, according to an exampleembodiment of the present inventive concepts.

Referring to FIG. 6A, the plurality of fins (e.g., a first fin F1, asecond fin F2, a third fin F3, and a fourth fin F4) are formed on thesubstrate SUB. The fins F1, F2, F3, and F4 are structures protrudingfrom the semiconductor substrate SUB. In some example embodiments, thefins F1, F2, F3, and F4 may be formed using an epitaxial growth processon the substrate SUB.

The first fin F1 and the second fin F2 (as well as the third fin F3 andthe fourth fin F4) may be formed to be spaced apart in the firstdirection D1. Further, the first fin F1 and the third fin F3 (as well asthe second fin F2 and the fourth fin F4) may be formed to be spacedapart in the second direction D2 crossing (or alternatively,perpendicular to) the first direction D1. Further, the fins F1, F2, F3,and F may be formed to be elongated in the second direction D2.

The substrate SUB may be a bulk silicon. For example, the substrate SUBmay be a silicon substrate, or may include a material other thansilicon, including but not limited to Ge, SiGe, SiC, GeP, GeN, InGaAs,GaAs, InSb, InAs, GaSb, and InP. The semiconductor substrate SUB may bea portion of a bulk silicon wafer. The substrate SUB may be asilicon-on-insulator (SOI). The substrate SUB may be a silicon portionof a Silicon-On-Insulator (SOI) wafer. In some example embodiments, thesubstrate SUB may refer to a semiconductor layer epitaxially grown on abase substrate.

Referring to FIG. 6B, the first bottom S/D region RX1 and the secondbottom S/D region RX2 are provided on the semiconductor substrate SUB.According to some example embodiments, the Bottom S/D regions RX1 andRX2 may be formed by etching the substrate SUB to a certain depth usingthe fins F1, F2, F3, F4 and a hard mask pattern (not shown) thereon(together with an additional mask pattern covering an entire area of thesubstrate SUB except for areas at which the first and second bottom S/Dregions RX1 and RX2 are to be defined) as an etch mask. Then, asemiconductor material layer may be epitaxially grown in recessed areasdefined by the etching, and doped with different dopants to form thefirst bottom S/D region RX1 for the PMOS FET and the second bottom S/Dregion RX2 for the NMOS FET, respectively.

The first and second bottom S/D regions RX1 and RX2 may be dopeddifferently by using an additional mask as an implant mask. For example,the first bottom S/D region RX1 in the PMOS FET area may be doped by ap-type dopants (e.g., Boron), and the second bottom S/D region RX2 inthe NMOS FET area may be doped by an n-type dopants (e.g., Arsenic orPhosphorus).

Referring to FIG. 6C, the gate patterns GP (e.g., a first gate patternGP1, a second gate pattern GP2, a third gate pattern GP3, and a fourthgate pattern GP4) may be formed on sidewalls of the fins F1, F2, F3, andF4, respectively. For example, the gate patterns GP may be formed tosurround sidewall of the fins F1, F2, F3, and F4, respectively. The gatepatterns GP each include a gate insulating layer (not shown) and a workfunction metal layer (not shown) on the gate insulating layer in someexample embodiments, the gate patterns GP may further include a cappingmetal layer (not shown) on the work function metal layer.

The gate insulating layer may include a high-k dielectric material.

The work function metal layer may include TiN. In some exampleembodiments, the work function metal layer may include titanium nitride(TiN) or titanium carbide (TiC). A work function of the work functionmetal layer for a VFET may be determined based on materialcharacteristics as well as a thickness of the work function metal layer.In some example embodiments, the work function metal layer may beimplemented to have different thicknesses depending on locations.

The capping metal layer may be subsequently formed on the work functionmetal layer. The capping metal layer may include at least one of TiC,TiAlC, or TiAl

Referring to FIG. 6D, the gate connecting structure PB is formed on thefirst gate pattern GP1, the second gate pattern GP2, the third gatepattern GP3, and the fourth gate pattern GP4 and connected thereto. Thegate connecting structure PB is a structure connecting the first gatepattern GP1, the second gate pattern GP2, the third gate pattern GP3,and the fourth gate pattern GP4 to each other. The gate connectingstructure PB and the first gate pattern GP1, the second gate patternGP2, the third gate pattern GP3, and the fourth gate pattern GP4 may bean integral structure, which includes respective portions correspondingto the gate connecting structure PB and the first gate pattern GP1, thesecond gate pattern GP2, the third gate pattern GP3, and the fourth gatepattern GP4. The gate connecting structure PB and the first gate patternGP1, the second gate pattern GP2, the third gate pattern GP3, and thefourth gate pattern GP4 may include a same material.

Although not specifically illustrated in the drawings, the first top S/Dregion (not shown), the second top S/D region (not shown), the third topS/D region (not shown), the fourth top S/D region (not shown) may beprovided on the first, second, third, and fourth fins F1, F2, F3, andF4, respectively

The first, second, third, and fourth top S/D regions may be formed byepitaxially growing p+ or n+ doped semiconductor layers on correspondingones of the first, second, third, and fourth fins F1, F2, F3, and F4,respectively. However, example embodiments of the present inventiveconcepts are not limited thereto. According to some example embodimentsof the present inventive concepts, the first, second, third, and fourthtop S/D regions may be formed by implanting desired dopants onto thefirst, second, third, and fourth fins F1, F2, F3, and F4, respectively.

Referring to FIG. 6E, the first top S/D contact structure CA1 is formedto cover both the first top S/D region on the first fin F1 and thesecond top S/D region on the second fin F2, and to be electricallyconnected to both the first top S/D region on the first fin F1 and thesecond top S/D region on the second fin F2. The second top S/D contactstructure CA2 may be provided to cover both the third top S/D region onthe third fin F3 and the fourth top S/D region on the fourth fin F4, andto be electrically connected to both the third top S/D region on thethird fin F3 and the fourth top S/D region on the fourth fin F4. Thefirst top S/D contact structure CA1 and the second top S/D contactstructure CA2 may include a conductive material such as metal.

The first top S/D contact structure CA1 and the second top S/D contactstructure CA2 may function as a horizontal conductive routing layer ofthe layout. The first top S/D contact structure CA1 and the second topS/D contact structure CA2 may be elongated in the first direction D2,and function as a first conductive routing layer running in the firstdirection D1 (e.g., a direction along which the first fin F1 and thesecond fin F2 (or the third fin F3 and the fourth fin F4 are arranged).

The gate contact structure CB may be formed on the gate connectingstructure PB such that the gate contact structure CB is electricallyconnected to the gate connecting structure PB. According to the exampleembodiment, the gate contact structure CB is formed on the gateconnecting structure PB at an area between the first fin F1 and thethird fin in the second direction D2. The gate contact structure CB maybe formed to be spaced apart from the first, second, third, and fourthfin F1, F2, F3, and F4 when viewed in a plan view, while being connectedto the gate connecting structure PB. The gate contact structure CB mayinclude a conductive material such as metal.

The first bottom S/D contact structure CR1 may be formed on the firstbottom S/D region RX1 to be electrically connected to the first bottomS/D region RX1. The second bottom S/D contact structure CA2 may beformed on the second bottom S/D region RX2 to be electrically connectedto the second bottom S/D region RX2. The first bottom S/D contactstructure CR1 and the second bottom S/D contact structure CR2 mayinclude a conductive material such as metal.

The first top S/D contact structure CA1, the second top S/D contactstructure CA2, the gate contact structure CB, the first bottom S/Dcontact structure CR1, and the second bottom S/D contact structure CR2may include a same material. The first top S/D contact structure CA1,the second top S/D contact structure CA2, the gate contact structure CB,the first bottom S/D contact structure CR1, and the second bottom S/Dcontact structure CR2 may be simultaneously formed in a same process. Asillustrated in FIGS. 4 and 5, top surfaces of the first top S/D contactstructure CA1, the second top S/D contact structure CA2, the gatecontact structure CB, the first bottom S/D contact structure CR1, andthe second bottom S/D contact structure CR2 may be formed at asubstantially same level with respect to (or alternatively, from) a topsurface of the substrate SUB.

Referring to FIG. 6F, the plurality of vias V0 are formed on the firsttop S/D contact structure CA1, the second top S/D contact structure CA2,and the gate contact structure CB, respectively.

Referring FIG. 6G, the plurality of metal patterns MP are formed tocorrespond to the plurality of vias V0. Although not illustrated in FIG.6G, at least some of the plurality of metal patterns MP may be formed tobe elongated in a direction (e.g., the second direction D2) along whichthe fins F1, F2, F3, and F4 are elongated so that the at least some ofthe plurality of metal patterns MP are electrically connected tocorresponding ones of the plurality of vias V0. Accordingly, the atleast some of the plurality of metal patterns MP may be connected tocorresponding ones of the gate contact structure CB and the first andsecond top S/D contact structures CA1 and CA2 through the plurality ofvias V0. Thus, the plurality of metal patterns MP functions as avertical conductive routing layer of the layout. The plurality of metalpatterns MP are elongated in the second direction D2 and functions as asecond conductive routing layer in the second direction D2 (e.g., adirection along which the first, second, third, and fourth fins F1, F2,F3, and F4 are elongated).

According to the example embodiment, an inverter standard cell includingthe PMOS FET and the NMOS FET each having a vertical channel implementedby two fins may be provided. In other words, an inverter standard cellincluding multi-gate NMOS VFET and multi-gate PMOS VFET may be provided.

According to the example embodiment, an inverter standard cell having agear ratio of 2:3 may be provided. In some example embodiments, gearratios (e.g., 1:2 or 3:4) may be implemented.

In a VFET, a fin vertically protruding from a substrate functions as achannel and a structure surrounding a sidewall of the fin functions as agate. Thus, the top S/D contact structure connected to the top S/D ofthe VFET and the bottom S/D contact structure connected to the bottomS/D of the VFET are less affected by an area occupied by the gate(meaning more design freedom or layout tolerance) compared toconventional planar or horizontal field effect transistors.

According the multi-gate VFET of the example embodiment, two or morefins function as a channel of the VFET, and gate patterns surroundingrespective fins functions as a gate and are connected to each otherusing a gate connecting pattern therebetween. Accordingly, themulti-gate VFET may provide a larger area for each of a gate contactstructure, a top S/D contact structure, and/or a bottom S/D contactstructure than a single-gate VFET or conventional planar or horizontalfield effect transistors

Thus, according to the example embodiment, a standard cell having a gearratio of m:n (where m and n are natural numbers, and n is greater thanm) can be implemented without using two crossing metal routing layers(e.g., a lower metal routing layer and an upper metal routing layer thatcrosses the lower vertical metal routing layer and is connected to thelower metal routing layer thorough a via). Thus, a standard cell havinga gear ratio of m:n (where m and n are natural numbers, and n is greaterthan m) can be implemented using a single metal routing layer.

FIG. 7A is a first modified layout of the inverter X1 standard cell ofFIG. 3, according to an example embodiment of the present inventiveconcepts. FIG. 7B is a cross-sectional view of the modified layout ofFIG. 7A taken along line VIIB-VIIB′, according to an example embodimentof the present inventive concepts.

Referring to FIG. 7A, the gate connecting structure PB is provided at anarea between the PMOS VFET and the NMOS VFET and connecting the first,second, third, and fourth gate portions GP1, GP2, GP3, and GP4 to eachother. The gate connection layer PB has a shape enclosing end portionsof each of the first, second, third, and fourth fins F1, F2, F3, and F4,which face each other in at least one of the first direction D1, thesecond direction D2, or a diagonal direction between the first directionD1 and the second direction D2.

As illustrated in FIG. 7A, to secure a sufficient space (which isdesired for implementing a uniform metal pitch) for a via V0 connectingto an underlying gate contact structure CB, the standard cell layout maybe modified such that the gate connecting structure PB includes anextended portion EP, which extends beyond a side of the bottom S/D inthe first direction D1.

In some example embodiments, at least one side of the gate connectingstructure PB may include an extension portion in the first direction D1.The extension portion (or extension area) may lie beyond an imaginaryline IL extending from a side of the first bottom S/D region RX1 (or thesecond bottom S/D region RX2) in the second direction D2. The extensionportion (or extension area) may lie beyond the imaginary line ILconnecting a side of the first bottom S/D region RX1 to a side of thethird bottom S/D region RX2 in the second direction D2.

Referring to FIG. 7B, a landing space for the gate contact structure CBto land on the gate connecting structure PB is enlarged due to theextended portion EP of the gate connecting structure PB. Thus, the viaV0 can be securely connected to the gate contact structure CB, and thusa uniform metal pitch may be implemented.

FIG. 8 is a second modified layout of the inverter X1 standard cell ofFIG. 3, according to an example embodiment of the present inventiveconcepts.

Referring to FIG. 8, in the case that a margin between the gate contactstructure CB and a neighboring gate connecting structure PB is tight, toavoid an undesired bridge between the gate contact structure CB and aneighboring gate connecting structure PB (not shown), the gateconnecting structure PB corresponding to the gate contact structure CBmay be formed such that a side of the gate connection structure CB isrecessed from (e.g., does not lie beyond) the imaginary line IL (whichis a line connecting a side of the first bottom S/D region RX1 to a sideof the third bottom S/D region RX2 in the second direction D2 in thefirst direction D1 when viewed in a plan view. For example, a firstlateral side of the gate connecting structure PB may lie inwardly withrespect to the imaginary line IL in the first direction D1 such thatamong two opposite sides of the gate connecting structure PB facing eachother in the first direction, one side of the gate connecting structurePB may be laterally between two opposing sides of the first bottom S/Dregion RX1 (or two opposing sides of the second bottom S/D region RX2)in the first direction when viewed in a plan view.

FIG. 9A is a third modified layout of the inverter X1 standard cell ofFIG. 3, according to an example embodiment of the present inventiveconcepts. FIG. 9B is a cross-sectional view of the modified layout ofFIG. 9A taken along line IXB-IXB′, according to an example embodiment ofthe present inventive concepts.

Referring to FIG. 9A, to secure a sufficient space for a via V0 to beconnected to an underlying gate contact structure CB, the standard celllayout may be modified such that the gate contact structure CB isextended in the first direction D1. Thus, the gate contact structure CBas shown in FIG. 7A may be elongated in the first direction D1 toward acenter of the gate connecting structure PB.

As shown in FIG. 9B, the modified layout illustrated in FIG. 9A providesan increased landing area for the via V0, and thus helps implement amore uniform metal pitch. Accordingly, a semiconductor device employingsuch layout may exhibit improved reliability.

FIG. 10A is a fourth modified layout of the inverter X1 standard cell ofFIG. 3, according to an example embodiment of the present inventiveconcepts. FIG. 10B is a cross-sectional view of the modified layout ofFIG. 10A taken along line XB-XB′, according to an example embodiment ofthe present inventive concepts.

Referring to FIG. 10A, to secure a sufficient space for a via V0 to beconnected to an underlying gate contact structure CB, the standard celllayout may be modified such that an additional top S/D contact structureCA′ is provided and merged with the gate contact structure CBillustrated in FIG. 9A. The additional top S/D contact structure CA′ isformed simultaneously with the top S/D contact structures for the topS/D regions. The additional top S/D contact structure CA′ may be formedto overlap the gate contact structure CB while not being connected toany of the top S/D regions.

As illustrated in FIG. 10B, the gate contact structure CB and theadditional top S/D contact structure overlap each other and provides anexpanded space (which is desired for implementing a uniform metal pitch)for the via V0 to land on the underlying gate contact structure CB. Themodified layout illustrated in FIGS. 10A and 10B provides an increasedlanding area for the via V0, and thus helps implement a more uniformmetal pitch. Accordingly, a semiconductor device employing such layoutmay exhibit improved reliability

According to the modified layouts described above, a sufficient spacefor a via desired for implementing a uniform metal pitch can beprovided. Thus, a standard cell having a gear ratio of m:n (where m andn are natural numbers, and n is greater than m) can be implemented

It should be understood that example embodiments described herein shouldbe considered in a descriptive sense only and not for purposes oflimitation. While some example embodiments have been particularly shownand described, it will be understood by one of ordinary skill in the artthat variations in form and detail may be made therein without departingfrom the spirit and scope of the claims.

What is claimed is:
 1. Semiconductor device comprising: a vertical fieldeffect transistor (VFET) including, a first fin, a second fin, a thirdfin, and a fourth fin protruding from a substrate, wherein the first finand the second fin spaced apart from each other in a first direction andelongated in a second direction crossing the first direction, the thirdfin and the fourth fin spaced apart from each other in the firstdirection and elongated in the second direction, a gate including afirst gate portion on a sidewall of the first fin, a second gate portionon a sidewall of the second fin, a third gate portion on a sidewall ofthe third fin, a fourth gate portion on a sidewall of the fourth fin,and a sixth gate portion connecting the first gate portion, the secondgate portion, the third gate portion, and the fourth gate portion, afirst top S/D including a first top S/D portion at a top of the firstfin and a second top S/D portion at a top of the second fin, and asecond top S/D including a third top S/D portion at a top of the thirdfin and a fourth top S/D portion at a top of the fourth fin; a gatecontact structure spaced apart from the first fin, the second fin, athird fin, and a fourth fin in the second direction when viewed in aplan view and connected to the sixth gate portion; a top S/D contactstructure connected to one of the first top S/D portion, the second topS/D portion, the third top S/D portion or the fourth top S/D portion, atleast one of the top S/D contact structure or the gate contact structureserving as a first conductive routing layer in the first direction; andmetal patterns on the gate contact structure and the top S/D contactstructure, the metal patterns configured to be connected to at least oneof the gate contact structure or the top S/D contact structure throughvias, respectively, the metal patterns serving as a second conductiverouting layer in the second direction.
 2. The semiconductor device ofclaim 1, wherein the first gate portion and the second gate portion arespaced apart by a first pitch in the first direction, the third gateportion and the fourth gate portion are spaced apart by the first pitchin the first direction, and the metal patterns are arranged by a secondpitch different from the first pitch in the first direction.
 3. Thesemiconductor device of claim 2, wherein a ratio between the first pitchand the second pitch is m:n, where m and n are natural numbers, and n isgreater than m.
 4. The semiconductor device of claim 3, wherein the m is2 and the n is
 3. 5. The semiconductor device of claim 3, wherein the mis 3 and the n is
 4. 6. The semiconductor device of claim 3, wherein them is 1 and the n is
 2. 7. The semiconductor device of claim 1, whereinwhen viewed in a plan view, at least one side of the sixth gate portionincludes an extension area in the first direction that lies beyond animaginary line, which is connecting a side of the first gate portion anda side of the third gate portion and extending in the second direction.8. The semiconductor device of claim 1, wherein when viewed in a planview, a side of the sixth gate portion is within an imaginary line inthe first direction, which is connecting a side of the first gateportion and a side of the third gate portion and extending in the seconddirection.
 9. The semiconductor device of claim 1, further comprising: afirst bottom S/D of the VFET enclosing at least a portion of the firstfin, the second fin, the first gate portion, and the second gateportion, when viewed in a plan view; and a second bottom S/D of the VFETenclosing at least a portion of the third fin, the fourth fin, the thirdgate portion, and the fourth gate portion, when viewed in a plan view,wherein the first bottom S/D and the second bottom S/D are grown byepitaxial on the substrate.
 10. The semiconductor device of claim 9,further comprising: a first bottom S/D contact structure; and a secondbottom S/D contact structure, which is spaced apart from each other inthe second direction, wherein each of the first bottom S/D contactstructure and the second bottom S/D contact structure are overlapping atleast of a portion of the first bottom S/D and the second bottom S/D.11. The semiconductor device of claim 9, when viewed in a plan view, thegate contact structure is elongated away from an imaginary line, whichis connecting a side of the first gate portion and a side of the thirdgate portion and extending in the second direction.
 12. Thesemiconductor device of claim 1, wherein a first fin, a second fin, athird fin, and a fourth fin are grown by epitaxial on the substrate. 13.The semiconductor device of claim 1, further comprising: an additionaltop S/D contact structure overlapping the gate contact structure and notconnected to the sixth gate portion.
 14. An inverter comprising: amulti-gate vertical field effect transistor (multi-gate VFET) including,a first fin and a second fin protruding from a substrate, the first finand the second fin spaced apart from each other in a second directionand elongated in a second direction crossing the first direction, afirst bottom S/D and a second bottom S/D of the multi-gate VFET on thesubstrate, each of the first bottom S/D and the second bottom S/Dsurrounding each of the first fin and the second fin, a first top S/Dincluding a first top S/D portion at a top of the first fin and a secondtop S/D portion at a top of the second fin, and a gate including a firstgate portion on a sidewall of the first fin, a second gate portion on asidewall of the second fin, and a third gate portion connecting thefirst gate portion with the second gate portion, the third gate portionoverlapping an end region of the first bottom S/D and the second bottomS/D; a gate contact structure spaced apart from the first fin, and thesecond fin in the second direction when viewed in a plan view andconnected to the third gate portion; a first top S/D contact structureconnected to the first top S/D portion, and a second top S/D contactstructure connected to the second top S/D portion, at least one of thegate contact structure, the first top S/D contact structure, or thesecond top S/D contact structure serving as a first conductive routinglayer in the first direction; and metal patterns on the gate contactstructure, the first top S/D contact structure and the second top S/Dcontact structure, the metal patterns configured to be connected to atleast one of the gate contact structure, the first top S/D contactstructure or the second top S/D contact structure, through vias, themetal patterns serving as a second conductive routing layer in thesecond direction.
 15. The inverter of claim 14, wherein when viewed in aplan view, at least one side of the third gate portion includes anextension area in the first direction that lies beyond an imaginaryline, which is connecting a side of the first gate portion and a side ofthe second gate portion and extending in the second direction.
 16. Theinverter of claim 14, wherein when viewed in a plan view, a side of thethird gate portion is within an imaginary line in the first direction,which is connecting a side of the first gate portion and a side of thesecond gate portion and extending in the second direction.
 17. Theinverter of claim 14, further comprising: a first bottom S/D contactstructure; and a second bottom S/D contact structure, which is spacedapart from each other in the second direction, wherein each of the firstbottom S/D contact structure and the second bottom S/D contact structureare overlapping at least of a portion of the first bottom S/D and thesecond bottom S/D.
 18. The inverter of claim 14, when viewed in a planview, the gate contact structure is elongated away from an imaginaryline, which is connecting a side of the first gate portion and a side ofthe second gate portion and extending in the second direction.
 19. Theinverter of claim 14, further comprising: an additional top S/D contactstructure overlapping the gate contact structure and not connected tothe third gate portion.